Down converters in wireless receivers perform a transformation of a radio frequency (RF) signal into a baseband signal centered at the zero frequency. In high performance equipment, digital down converters are used, making it necessary to convert an analog RF signal into a digital signal. Typically, a high speed ADC is used because of the high frequency of the RF signal.
High speed analog to digital converters are built as composite ADCs that consist of a number of interleaved sub-ADCs with a common input and sequential timing. In general, the amplitude and phase frequency responses of the different sub-ADCs are not identical, resulting in specific signal distortions, for example, the appearance of spurious frequency components. To prevent these distortions, equalization of the responses of the sub-ADCs is used (see, for example, U.S. Pat. No. 7,408,495).
A block diagram of a conventional digital down converter with an equalizer, is shown in FIG. 1. An RF signal applied to the input of an ADC, is transformed into a digital signal. The misalignment of the frequency responses of the sub-ADCs of the ADC, is corrected by an equalizer. An I/Q demodulator is constructed using two mixers with the same local oscillator frequency and with a phase difference of 90□. Low pass filters with following decimators produce two outputs labeled In-Phase (I) and Quadrature (Q).
The ADC equalizer and low pass filters in the block diagram of FIG. 1 are built usually as a conventional finite impulse response (FIR) filter. The most resource-consuming components of FIR filter are multipliers. Because of the difference between the RF signal frequency (usually several GHz) and the frequency of operation of present-day FPGA (up to 200-250 MHz), each multiplication in the FIR filter is carried out by a group of multipliers connected in parallel. The required number of multipliers becomes the main reason that makes it necessary to use in the equalizer design, more FPGAs and/or FPGAs of bigger size or, in some cases, makes the real time equalizer design impossible.
In a WiGig LAN communication system, it is suggested, for example, to use a super-heterodyne architecture with an intermediate frequency of 5.8 GHz. To process signals in such a frequency range, an ADC of a down converter should have a sample rate of 20 Gs/s or higher. With an FPGA frequency of operation of 200 MHz, each multiplication in an FIR filter requires 20000/200=100 multipliers operating in parallel, with an average length of an equalizer having about 80 taps. This means that implementing an equalizer requires 80×100=8000 multipliers. Such a number exceeds the resources of any available FPGA, with a consequence that a real time digital down converter under those described conditions is not possible.
It is possible to reduce to some extent, the required number of multipliers in the conventional down converter, of the type shown in FIG. 1, by embedding decimation within low pass filters between a shift register of an FIR filter and the multipliers (see, for example, J. G. Proakis and D. G. Manolakis, “Digital signal processing”, p. 794). In such a design, the multiplications in the low pass filters are performed at lower sampling rates, with a consequent possibility to cut down the required number of multipliers. However, the amount of multipliers in the equalizer far exceeds the amount of multipliers in the low pass filters. For this reason, a reduction of the number of multipliers only in the filters, does not lead to a substantial decrease of the total number of multipliers in the down converter. In the block diagram of FIG. 1, equalization is carried out before down conversion by a unit that is common for both branches I and Q.